(1) Field of the Invention
The present invention generally relates to electromagnetic signal acquisitions systems and specifically to optimizing a signal acquisition system that utilizes parallel processing channels.
(2) Description of the Prior Art
The electromagnetic signal receiving system described in U.S. Pat. No. 6,466,167, by the present inventor (Dr. Donald Steinbrecher) is incorporated herein by reference. The receiving system is a parallel processing system in which signal energy of a frequency band of analog electromagnetic signal space is divided equally among parallel channels. As a minimum, each parallel channel comprises an amplifier to lower system noise followed by an analog-to-digital converter (ADC) to create a digital image of the incident analog signal energy. The total signal energy is divided equally among the parallel channels so that each channel contains a portion of the energy from all signals in the frequency band of analog electromagnetic signal space.
The plurality of digitized channels is recombined in the digital signal processing domain to create a single digital image of the frequency band of analog signal space. It is stated in U.S. Pat. No. 6,466,167 that the minimum detectable signal (MDS) sensitivity is degraded by only a minor amount that is determined by the signal energy lost in the process of dividing the signal energy across a plurality of “p” identical signal channels.
It is further stated that the process of recombining the plurality of digital data streams in a digital signal processor can be accomplished without degrading the spurious-free dynamic range (SFDR) of the system. This is because the SFDR of a digital signal processor is directly related to the number of mantissa bits carried for each digital word in the processor. An empirical relationship between the SFDR and mantissa bits is that the SFDR increases approximately 5 dB for each mantissa bit. Thus, a digital signal processor (DSP) engine maintaining 32 mantissa bits would have a SFDR of at least 160 dB.
The programmable logic devices used for combining the plurality of digital signals and field programmable gate arrays (FPGA) allow the number of mantissa bits to be specified in the programmable logic. It follows that the digital combining process can be programmed to avoid degrading the SFDR regardless of how large a value of p is necessary to meet the mission SFDR requirement.
There are some items of concern with the above referenced art that were discovered as the system was operated. It was found that unexpected spurious responses that degraded overall performance were caused by imperfections in the ADCs used in the first p=12 system. It was concluded that such spurious responses could be expected in future systems emulating the same architecture.
The present invention addresses the above and other problems in a manner not shown in the prior art. Accordingly, those skilled in the art will appreciate the present invention.